For this part you are required to design a sequential circuit that emulates parts of an instruction interpretation cycle. The machine has a collection of that achieves the following behavior $($all data inputs$/$outputs of this circuit are single bits$)$:

Inputs: indirect, program$-$check, C$1,$ clock

Outputs: fetch, decode, indirect, execute, trap, S$1,$ S$2$

States: fetch, decode, indirect, execute, trap