Question: ( g ) Name the module getval: output y is a 1 2 - bit signal. Input a is a 3 - bit signal. Your

(

)

Name the module getval: output y is a

12 -

bit signal. Input a is a

3 -

bit signal. Your module should shift a left by two bits

(

.

.,

append two

0

2

0)

and then sign extend a into the remaining bits. Recall that to replicate a bit from another signal use brackets: for example, the following replicates the second bit of a

,

[2], 3

times:

{3 {

[2]}} .

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