General Statement: Implement function F(A,B,C,D) = Sum(0,1,7,13,15) +Dont Cares(2,6,8,9,10) by only using two-level logic. Thus, you are to draw the circuit using the Xilinx ISE Schematic Editor, and then simulate it using the Xilinx ISE Simulator. You are to get a printout of the Simulation results (i.e. the timing diagram).

Also, you are to provide:

1. Function table for the above function

2. K-map simplification

3. Verilog test bench code