Question: given a 4 way set associative cache row X has all valid bits set to one, meaning all blocks in row X have valid data.

given a

4

way set associative cache row X has all valid bits set to one, meaning all blocks in row X have valid data. when another access to row X occurs and the tag does not match any og the four tags, it is called a

(

capacity

,

compulsory, or conflict

)

miss

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