Given an 8 bit processor with general purpose register set R r 0 , r 1 , r 2 , r 4 , r 5 , r 6 , r 7 , a set of memory variables M m i i i n 1 , 2 , cdots and a set of all possible immediate values I The instruction set of the target machine contains the following instructions MOV x , Y xlarrY, ADD x , Y xlarrx Y , SUB x , Y xlarrx Y , MUL x , Y x l a r r x Y DIV x , Y xlarr x Y , C M P x , Y compares the values in x and Y J G T L l jump to level L l if x Y after the execution of a C M P x , Y where lin 1 , 2 , cdots J M P L l unconditional jump to level L l , where lin 1 , 2 , cdots For MOV if xinR then YinR M I if xinM, then YinR For ADD,SUB , M U L , DIV and C M P xinR and YinR M I An m i is required whenever there is a shortage of registers during code generation ( a ) Write the 3 address intermediate code the following code fragment 8

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Question: Given an 8 - bit processor with general purpose register set R = { r 0 , r 1 , r 2 , r 4

Given an

8 -

bit processor with general purpose register set

R = {r_{0}, r_{1}, r_{2}, r_{4}, r_{5}, r_{6}, r_{7}},

a set of memory variables

M = {m_{i} | i i n {1, 2,

cdots

}}

and a set of all possible immediate values I. The instruction set of the target machine contains the following instructions:

MOV

x, Y

;xlarrY, ADD

x, Y

;xlarrx

+ Y,

SUB

x, Y

;xlarrx

- Y,

MUL

x, Y

;

x l a r r x^{* *} Y

DIV

x, Y

;xlarr

\frac{x}{Y}, C M P x, Y

; compares the values in

x

and

Y

J G T L l -

jump to level

L l

x > Y

after the execution of a

C M P x, Y

; where lin

{1, 2,

cdots

}

J M P L l -

unconditional jump to level

L l,

where lin

{1, 2,

cdots

}

For MOV if xinR then YinR

M

I; if xinM, then YinR.

For ADD,SUB

\frac{,}{M} U L,

DIV and

C M P

;xinR and YinR

M

m_{i}

is required whenever there is a shortage of registers during code generation.

(

)

Write the

3 -

address intermediate code the following code fragment.

[8]

Given an 8 - bit processor with general purpose

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