Given the following instruction sequence for the MIPS processor with the standard $5$ stage pipeline,

addi $$10,$$$0,4$

lw $,$$$2,0($$$10)$

add $,$$$2,$$$2,$$$2$

sw $,$$$2,4($$$10)$

a$.$ Show the data dependences between the instructions above by drawing arrows between dependent

instructions $($only show true$/$data dependencies$).$

b$.$ Assuming forwarding support, in what cycle would the store instruction write back to memory?

Show the cycle by cycle execution of the instructions as they execute in the pipeline. Also, show any

stalls $($bubbles$)$ if necessary.

addi:

lw:

add:

sw:

c$.$ For the MIPS pipeline, what is the earliest stage that the control hazard due to the beq rs$,$ rt$,$ label

instruction can be resolved?

i$.$ Specify the stage and explain why it can be resolved in that stage but not earlier.

ii$.$ How many cycles does the pipeline stall due to control hazards?