Given the following MIPS code segment, at the given decimal byte addresses, executing on a single cycle processor: 312 loop: beq $t1, $t2, next

316 addi $t3, $t3, 1

320 sub $s2, $s2, $t3

324 or $s1, $s2, $t3

328 and $s1, $s2, $t3

332 add $s2, $s2, $t3

336 j loop

340 next: sw $t3, 4($s2)

For each answer you enter, include the correct number of bits e.g. do not omit any leading zeros.

a) List the exact bit values that will be sent to the sign extender when the BEQ instruction is executing:

b) List the exact bit values that will be sent from the shifting unit to the concatenator when the J instruction is executing:

c) List the exact bits from the instruction that will be sent to the ALU control when the AND instruction is executing:

d) List the exact bits that will be input to the Register File for Read Register 1 when the SW instruction is executing: