Given the FPGA in Figure $3$ below, implement logic for the next state n$0=$F$($s$1,$ s$0,$ a$,$ b$)$ from Figure $1($The A$,$ B$,$ C and D in Figure $1$ are different from the $\text{'}$A$\text{'}$ and $\text{'}$B$\text{'}$ in Figure $3).$The combinational logic implements the FSM shown in Figure $2.$ Fill in the left$-$hand table $($i$.$e$.,$ D$1$ output$)$ in CLB$-$A with the portion of the logic function that includes s$1\text{'}$s$0\text{'}$ and right$-$hand table $($i$.$e$.,$ D$0$ output$)$ with the portion of the logic function that involves s$1\text{'}$s$0$ and s$1$s$0\text{'}$ for the input variables shown for CLB$-$A$.$

Note: Compute the minterms for n$0$ function.

PLEASE EXPLAIN AND SOLVE BOTH TABELS.