Half$-$cycle write back $($or fast register$)$ file is present

Stall capability based on non$-$forwardable data hazard detection

Resolves branches in the Decode stage. If the branch is found to be NOT taken in the decode stage$($Prediction$=$Reality$),$ no bubble is introduced into the pipeline on account of the branch instruction. However, if a branch turns out to be taken, we pay the price in the form of an extra clock cycle.

In this code example, the branch is NOT taken for $13($l$.$e$.5I=4),$ so the next instruction $($addi$)$ will be executed ofter the beq instruction.

Fill in the table to show how the pipeline progresses:

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13],[11$: add $1,2,3,$F$,$D$,$X$,$M$,$W$,,,,,,,,],[12$: $1$d $4,(x1),,7,1,$D$,$D$,*,$m$,$W$,,,-,,],[13$: beq $5,4,14,,,$F$,,,,,,,,,,],[14$: addi $x6,$ x$6,1,,,,,,,,,,,,,],[15$: bne, $6,7,$ exit,,,,,,,,,,,,,$]]$