he and gate primitive in Verilog accepts two inputs. To create a 4-input and gate, several 2 -input gates are combined: Using Verilog, model the 1-bit, 4-input and gate at the gate level (i.e., use Verilog's 2-input and gates and interconnect them with wires). Write the testbench code, and test the design with eight input combinations. Include a screenshot of the console output in your pdf document. Include the design and testbench code ( text file(s)) in the zip file. Model the 4-input and gate at the register transfer level (RTL) (i.e., use the assign statement). Using the same testbench code as part (a), test the design. Since it's the same, you do not need to submit the testbench design code for this part. Include a screenshot of the console output in your pdf document. Include the design code in the zip file