Starting from basic components, primitives, write full structural code for this ALU as follows:

A) Write Verilog structural code for:

* Full Adder (fullAdder), you can create you full adder using logic gates or by first building half adder then instantiating this half adder two times with OR gate. (you are free to select any method to build this full adder)

* 4 bits Adder Subtractor by instantiating Full Adder (fullAdder) you built in step above and XOR gates.

* 4 bits bitwise AND.

* 2 to 1 MUX with one, one bit select line, and each input is 4 bits, by instantiating one-bit mux you built in lab 1.

B) Write Verilog structural code for the given ALU by instantiating the units you built in steps above (ALU schematic is repeated for convince)

Don't forget to write testbench code for the ALU, you should use at least 4 different sets of inputs and verify the correctness of your entire code, you are to use $monitor instruction in your testbench.

please provide clear screen shots of the ALU testbench results (waveform)

Below circuit represents a given ALU which implements the following operations Add, Sub, bitwise AND. This ALU accepts two binary numbers as inputs A and B, 4 bits each and one 2 bits Control line, it also has one 4-bits output Result and one 1-bit output Overflow The ALU functionality and schematics is shown in the provided figure and function table: SUM CCout