Help me with this Xillinx Vivado VHDL code project please!!

UART Project Evaluation Rubric:

1. Transmitter Data Path integrating the following sub-models

-Eleven bit Transmitter UniveralShift Register Model and Test Bench Model

-Eight bit Transmitter Buffer Register Model and Test Bench Model

2. Transmitter Controller FSM

3. UART Receiver Model integrating receiver Data Path and Controller

4. Receiver Data Path integrating the following sub-models

Eleven bit Receiver Universal Shift Register Model

Eight bit Receiver Buffer Register Model

5. Receiver Controller FSM

6. UART Transmitter Model integrating transmitter Data path and Controller

7. Test Bench Model for UART Transmitter instance sending 8-bits of data to a UART Receiver instance