Hi. I run this code with yosys 0.9.0 in EDAplayground but i clicked the show diagram after run but i take error of .svg file does not find how to make suitable for showing diagram?

2. Test Bench: module tb_SequenceLock; reg A0,A1,A2,A3,A4,A,A6,A7,A,A,j wire Lock; // Instantiate the SequenceLock module SequenceLock UUT ( .A0(A0),.A1(A1),.A2(A2),.A3(A3),.A4(A4), .A5(A5),.A6(A6),.A7(A7),.A8(A8),.A9(A9), . Lock(Lock) ); // Initial stimulus initial begin // Incorrect passcode entry with a delay of \#5 \# A=1;A1=2;A2=3;#5; A0=0;A1=0;A2=0;#5; AO=4;A1=5;A2=6;#5; A0=0;A1=0;A2=0;#5; A=7;A1=8;A2=9;#5; A=0;A1=0;A2=0;#5; // No key pressed #A0=0;A1=0;A2=0;#5; // Correct passcode entry \#5 A0=0;A1=1;A2=8;#5; \$stop; // Stop simulation end endmodule