How many latches will be generated after synthesis? Provide a brief explanation for

your answer.

entity add$\_$sub is

Port $($ a$,$b: in integer;

op: in std$\_$logic;

result : out integer$)$;

end add$\_$sub;

architecture Behavioral of add$\_$sub is

begin

process $($a$,$b$,$op$)$

begin

if $($op $=\text{'}1\text{'})$ then

result a$+$b;

end if;

end process;