Question: How to write a test bench for this VHDL Code? a) Design Purpose The purpose of this project is to generate pseudorandom numbers and display

How to write a test bench for this VHDL Code?

How to write a test bench for this VHDL Code? a) Design

Purpose The purpose of this project is to generate pseudorandom numbers and

a) Design Purpose The purpose of this project is to generate pseudorandom numbers and display corresponding hamming code on LED's present on Spartan3E FPGA board. Use XA4X 1 linear feedback shift register (LFSR) as pseudorandom generator circuit. The four D-Flip Flops used in LFSR circuit output 4-bit output values at 1 Hz in the free running mode. .When SW1 switch is pressed, the finite state machine (FSM) will be in the idle state and the LED is blank. .When SW2 switch is pressed, the 4-bit LFSR message will be displayed on four LEDs. .When SW3 switch is pressed, the (7, 4) hamming code will be displayed on seven LEDs

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