How would you implement the following module to pe implemented onto a spartan 3 board for testing? ucf file) module sram ctrl input wire clk, reset Il to/from man system input wire mem, rw. input wire [17:0] addr. input wire [15:0] data_f2s. output reg ready. output wire 15:0) data 21 data 21 // to/from sram chip output wire [17:0) ad output wire we noen // sram chipa inout wire [15:0) dio_a. output wire cean, banban r. // symbolic state declaration localparam 12:01 idle - 36000. rd1 - 35001 rd23'0010. wr13b011. 23b100; 11 signal declaration reg 2:0 state reg, state next; reg (15:0) data f2s reg, data f2s_next; reg (15:0) data s2f reg. data 21 next: reg (17:0) addr_reg, addr_next: reg we but, cebul, tri_but: reg we reg. oe reg, tri reg: // body // FSMD state & data registers always {posedge clk, posedge reset) if (reset) begin state reg idle: addr_reg