Help me solve question 5 and 6

3) The objective of this problem is to learn about building custom counters. Design a block diagram of a counter that counts from 0 to 5 and then resets to 0. When it gets to 5 generate an output of Z=1, for all other cases Z=0. Use a synchronous counter. Draw a block diagram showing all gates and flip-flops required. Turn in a pdf image of your design. See Lecture 8 section 3 for details of synchronous and asynchronous counters. 5) Implement counter described in problem 3, using a Verilog procedural code. Turn in code and simulation verification wave form snapshots. Show it counting through two full cycles, that would be 12 clock positive edges. Show the input clock, the count. See Lecture 8 Section 4 slide 53. Make sure you use a behavioral model procedural code for credit. 6) View the RTL netlist flow diagram for your design in problem 5. Capture the image and save to pdf. How is it different than the block diagram shown above? 3) The objective of this problem is to learn about building custom counters. Design a block diagram of a counter that counts from 0 to 5 and then resets to 0. When it gets to 5 generate an output of Z=1, for all other cases Z=0. Use a synchronous counter. Draw a block diagram showing all gates and flip-flops required. Turn in a pdf image of your design. See Lecture 8 section 3 for details of synchronous and asynchronous counters. 5) Implement counter described in problem 3, using a Verilog procedural code. Turn in code and simulation verification wave form snapshots. Show it counting through two full cycles, that would be 12 clock positive edges. Show the input clock, the count. See Lecture 8 Section 4 slide 53. Make sure you use a behavioral model procedural code for credit. 6) View the RTL netlist flow diagram for your design in problem 5. Capture the image and save to pdf. How is it different than the block diagram shown above