i have already done question 1 i need help understanding question 2. what does it mean split into two separate stages of 50 each from my understanding. It would still be the same for a pipe lined processor so there wouldn't be any resulting speed up.

CS 270 Introduction to Computer Architecture II Spring 2023 Homework 2 Ouestion 1. Assume that the MIPS stages have these latencies (in ps): a) [3 Points] What is the clock cycle time for a nonpipelined processor? b) [2 Points] What is the clock cycle time for a pipelined processor? Question 2. Suppose that we modified the pipelined processor described in Question 1 such that all data memory reads and memory writes were split into two separate stages of 50 ps. each. a) [1 Points] Would the overall throughput increase or decrease in the modified architecture? b) [2 Points] What is the cycle time of modified pipelined processor? c) [2 Points] What would the resulting speedup, if any