I need help with this problem, my professor hasnt gone over parity but wants us to research how to preform this. I looked it up and still dont quite understand. Can you please, comment code. Also I am working in Verilog Vivado. Thanks in advance

1-2. Write a task called calc_even parity which will take an 8-bit number, and compute and return parity. Write a module, called calc even parity task, which calls the task with the operand received via the input port and outputs the result. Use the provided testbench, calc_even_parity_ task tb.v, that displays the result using $display system task. Simulate the design and verify the functionality. 1 time scale 1ns / 1ps /Module Name: calc even parity task tb 6 module calc even parity task tb 7 reg 17:0] ain; 10 wire parity; integer k 13 14 calc even parity task DUT (.ain (ain), .parity (parity)) 15 16 17begin initial $display ("ain-th, time-%t", ain, parity, $time); parity-%b , k=k+1) at 20p for (k=0; 21begin k