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1-C3-PLO3 (20 marks Question 3: For the following instructions lw $t0,($zero) #load final count from memory address o lw $t1, 4($zero) # initialize counter $t1 from address 4 lw $t2, 4($zero) #initialize St2 from address 4 repeat: beq $t0,$t1, exit # check if final count reached add $t1,$t1,$t2 #increment the counter by the amount read from address 4 sw $t1, 0($t1) #store to the address with the same value j repeat exit: j exit Initial value of memory is given in table below Mem Address Content 0 8 4 2 8 2 12 00 ALU 4 nsec Let's assume that the operation time for the following units is in following table 2 Components Memory Reg File Sign-Extend, PC accesses and wires Time of operation 4 nsec 2 nsec Onsec For this information, compute the CPI for a) Single cycle architecture execution (2) b) Multi cycle architecture execution c) Single cycle pipelined execution without hazard avoidance mechanism (5) d) Single cycle pipelined execution with forwarding mechanism to remove data hazard (10) 1-C3-PLO3 (20 marks Question 3: For the following instructions lw $t0,($zero) #load final count from memory address o lw $t1, 4($zero) # initialize counter $t1 from address 4 lw $t2, 4($zero) #initialize St2 from address 4 repeat: beq $t0,$t1, exit # check if final count reached add $t1,$t1,$t2 #increment the counter by the amount read from address 4 sw $t1, 0($t1) #store to the address with the same value j repeat exit: j exit Initial value of memory is given in table below Mem Address Content 0 8 4 2 8 2 12 00 ALU 4 nsec Let's assume that the operation time for the following units is in following table 2 Components Memory Reg File Sign-Extend, PC accesses and wires Time of operation 4 nsec 2 nsec Onsec For this information, compute the CPI for a) Single cycle architecture execution (2) b) Multi cycle architecture execution c) Single cycle pipelined execution without hazard avoidance mechanism (5) d) Single cycle pipelined execution with forwarding mechanism to remove data hazard