I would like the answer, but presented as a data path in a MIPS single$-$cycle architecture

Instruction Memory: $200$ps

Data Memory: $250$ps

Register File: $160$ps

ALU: $120$ps

Sign$-$extend: $10$ ps

Shift$-$Left $2$:$15$ps

Mux: $35$ps

Adders: $45$ps

PC and other circuits: negligible delays