Identify a true statement about the given Verilog code snippet. module Example (f,x,h) input h,; output reg f; always @ (h,s) begin fog & h; end endmodule O a. If g = 1 and h = 0, then f = 0. The change in h's value to 1 will not execute the procedure; thus, f = 0 O b. When none of the inputs change, the always procedure does not execute Oc. When none of the inputs change, the always procedure still executes Od. If g = 0 and h = 0, then f = 0. The change in g's value to 1 causes the procedure to execute f = 1