Identify AAA and ZZZ in the given VHDL code snippet. Given: Inputs: a$,$ Outputs: $\backslash (\backslash$mathrm$\{$B$\}(8)\backslash ),$ and Variables: $\backslash (\backslash$mathrm$\{$C$\}(8)\backslash ).$

$```$

entity Pulsegenerator$\_$HLSM is

port $($clk$,$ rst : in std$\_$logic;

a : in std$\_$logic;

B : out unsigned$(7$ downto $0))$;

end Pulsegenerator$\_$HLSM;

architecture Behavior of Pulsegenerator$\_$HLSM is

begin

process $($AAA$)$

ZZZ

$...$

end process

$```$

$\backslash ($ A A A$=$C $\backslash )$

ZZZ $=$ B : in unsigned$(7$ downto $0)$;

$\backslash (\backslash$mathrm$\{$AAA$\}=\backslash$mathrm$\{$clk$\}\backslash )$

ZZZ $=$ variable C : unsigned$(7$ downto $0)$;

$\backslash (\backslash$mathrm$\{$AAA$\}=\backslash$mathrm$\{$clk$\}\backslash )$

ZZZ $=$ variable $\backslash ($ C $\backslash )$ : unsigned$(7$ upto $0\backslash ()\backslash )$;

$\backslash ($ A A A$=$a $\backslash )$

ZZZ $=$ B : in unsigned$(0$ upto $7)$;