If a computer based on CPU with a $2-$stage pipeline is going to execute the instructions given

in Table$1,$ use a diagram to illustrate the operations performed by the EU$,$ BIU and the BUS

with respect to time during the execution of these instructions.

The status for EU$,$ BIU and the BUS could be Busy, Fetch, Execute, Read and Write. You can

assume that the execution time of an instruction is longer than a read or write operation.