Question: If you could just do the AND gate, that would be awesome Do this in some nice looking drawing package using gate level design. i.e.

If you could just do the AND gate, that would be awesome

If you could just do the AND gate, that would be awesome

Do this in some nice looking drawing package using gate level design. i.e. show gates! Logic diagrams, NOT wiring diagrams. I would again suggest that you maybe use ALTERA's Quartus-II software (WINDOWS only). I have been using draw.io which I think is awesome on the MAC. VISIO is probably another good choice on WINDOWS. You now have designed one 4-bit register. Your initial ALU design will have the following instructions ADD NOT AND OR We may add more instructions later in the semester. Hints: What are the inputs of this block? What are the outputs of this block? Are there any timing controls necessary? Turn in a jpg or other easily read picture of your complete design Assume that the ALU is fed by two 4-bit registers, TempA and TempB. Assume the output feeds another register we will call the 4-bit Accumulator. TEMP B TEMP A Load TEMP A Load TEMP B AND NOT ALU OR Accumulator Load ACC Do this in some nice looking drawing package using gate level design. i.e. show gates! Logic diagrams, NOT wiring diagrams. I would again suggest that you maybe use ALTERA's Quartus-II software (WINDOWS only). I have been using draw.io which I think is awesome on the MAC. VISIO is probably another good choice on WINDOWS. You now have designed one 4-bit register. Your initial ALU design will have the following instructions ADD NOT AND OR We may add more instructions later in the semester. Hints: What are the inputs of this block? What are the outputs of this block? Are there any timing controls necessary? Turn in a jpg or other easily read picture of your complete design Assume that the ALU is fed by two 4-bit registers, TempA and TempB. Assume the output feeds another register we will call the 4-bit Accumulator. TEMP B TEMP A Load TEMP A Load TEMP B AND NOT ALU OR Accumulator Load ACC

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