Im stuck on a hw question about a binary counter in verilog code. I am using eda playground. This is what I have so far.

Binary counter 0->1->2->3->0-1-92. . And a reset From 0 . Upload your design in design.sv window and add your testbench in testbench.sv window .Please use "finite state machine" method 1 tinescale 1 ns/100 ps 3 module BinaryCount Down; s III/change start here: this is the deisgn part SVVenilog Testbench VIIThis is the library 3 module f, a)i 4 input a s output f 61 assign #0.2 f-~a; 7 endmodule 6 wire ty: //hint: the connctions between nodules, set t 7 reg t.a, tb; I/hint: variable you set signals, set them reg o illchange End here 9 module NANDZ (f, a, b): 10 input a, b; 11 output f 2 wire t; 13 nand (t,a,b): 141 assign 0.3 f-t; 15 endmodule 12 initial Sdumpfile("dump. ved") Sdumpvars (1) 17 module AND2 (f, a, b)i 18 input a, bi 19 out put fi 20 wire t; 21 and (t,a,b)t 22 assign #0.5 f-t; 23 endnodule 111/change start here: this the test part 25 module NORZ (f. a, b) 26 input a, b 27 output f 2 wire t; 29 nor (t,a,b) 30 assign so.3 f- ti 31 endmodule t.a-1'b1 /II/change End here Sdumpoffi 33 module OR2 (f, a, b) 4 input a, b s output fi 6 wire ti 37 or (t,a,b)i 381 assign#0.5f" t; 39 endmodule 36 endsodule 41 module XOR2 (f, a, b)i 42 input a, b 43 out put fi wire t 45 xor (t,a,b)i 46 assign #0.3f-t; 47 endsodule 49 module XNOR2 (f, a, b) 50 input a, b 51 output fi wire ti xnor (t,a,b) 54 assign 80.3f ti s5 endnodule