Implement $8$ bit multiplier in FPGA

I need the verilog code

And to show the steps of design $,$ including FSMD $($ Finite State Machine Diagram $),$ the data path and control unit

Use this algorithm

if $($a$\_$in $=0$ or b$\_$in $=0)$ then$\{$

$r=$;

else$\{$

$a=a_{-}$in; $,n=b_{-}$in; $r=0$;

$r=r+a$;

$n=n-1$;

if $)=(0$ then $\{$goto stop; $\}$

else $\{$goto op; $\}$

$\}$

r$\_$out $=r$;