I need a verilog code to implement $8$ bit multiplier in FPGA.

show all design steps

FSMD$,$ ALU

datapath and control unit

using this algorithm

if $(a_{-}$in $=0$ or b$\_$in $=)$ then$\{$

$r=$; $\}$

else $\{$

$a=a_{-}$in; $,n=b_{i}n$;$,r=0$;

$r=r+a$;

$n=n-1$;

if $)=(0$ then $\{$goto stop; $\}$

else $\{$goto op; $\}$

$\}$

$r_{?}$out $=r$;