Implement an 8-bit register in VHDL/Verilog using Model Sim software. Show two test cases for data read

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Question:

Implement an 8-bit register in VHDL/Verilog using Model Sim software. Show two test cases for data read and write into the register.

The register has an enable and reset signal. When the reset is high the register should be cleared. When the enable is high and reset is low, data should be written into the register.