Implement the following to be gate level using D-flip-flops, full adder, and 2x1 multiplexers

Behavioral model of I-bit serial adder module serial _ adder (x, y, S, Clock, Clear); input x,y,C10ck,C1ear; output S; reg D; // simulating D flip-flop wire CI; assign {C, S} = X+Y+D; assign CI Clear ? O always a (negedge Clock) D endmodule c; dataflow binary adder // behavioral 2x1 multiplexer // load D on negative edge