Implement the most efficient Design for a 3-to-8 binary decoder. Find the cost ( chart below) and worst-case delay of your design.

Build your decoder and choose the design with minimal delay. (You cannot use a primitive logic gate larger than four inputs.) Clearly state how you calculate that delay and how you decided to balance between delays of its many outputs.

GATE \\ COST \\ DELAY ( x = # of Gates)

NOT \\ $0.02 \\ 1

tri-state inverter \\ $0.03 \\ 1.5

NANDx \\ $ {3 + (x 2)^2} \\ 2

NORx \\ $ {4 + (x 2)^2} \\ 2

ANDx \\ $ 3 + (x 1)^2 \\3

ORx \\ $4 + (x 1) ^2 \\3

XORx \\$ 7 + (x 2)^2 \\3

XNORx \\ $ 7 + (x 2)^2 \\3

This is as specific as I can make it. This was all I was given.