$*($Important$)**$Please solve this problem in detail and make sure to draw the state diagram of FSM and solve the verilog HDL code$*$We would like to design a prime number checker that works as shown in $($Figure $8)$

$($Figure $8)$

The input is clk$,$ reset, and the output is q$[3$:$0],$ pn$,$ done

clock$$ positive edge$-$triggered

$q[3$:$0]$ increases the value from $2$ to $15$ by $1$ for each clock period

If $q[3$:$0]$ is a prime number, $pn=1$ or $pn=0$

When $q[3$:$0]$ reaches $15,$ wait until done $=1$ for $1$ clock period and then reset$=1$ for other times is done $=0$ for

After $q[3$:$0]$ reaches $15$ and done$=1,$ if reset $=1,q[3$:$0]$ becomes $2$ and repeats the above again $($Precautions$)$

When you get a prime number, you need to check its mathematical definition, which is a multiple of another number. $2,3,5...$ and

We know the prime number in advance, so if we code it in the form of substituting it$,$ we don't give you a score.

This isn't about checking Verilog HDL grammar, so if you've approached coding the right way Verilog HDL Grammar is ignored and points are given.

$(1)$ Draw the state diagram of the FSM from the prime number checker in $($Figure $8).(20$ points$)$

$(2)$ Describe the FSM as Verilog HDL in the prime number checker in $($Figure $8).(20$ points$)$