In CPU$-$OS simulator instructions are processed through $5$ stages fetch, decode, read operands, execute and write results. Each instruction takes $5$ clock cycles. Instruction fetch takes additional $2$ clock cycles in case of cache miss. Execute stage of MUL takes $6$ clock cycles instead of $1$ clock cycle. Block of direct mapped cache can store $4$ instructions. Following code snippet is executed in the simulator: $[10$ Marks$]$MOV #$5,$R$00$MOV #$10,$R$01$ADD R$00,$R$01$MUL R$00,2$HLTAssume cache is initially empty. Find following:a$)$ Hit ratiob$)$ List of instructions with cache missc$)$ Total clock cyclesd$)$ CPIe$)$ Data hazard in the snippet if any.