In Part A$,$ you created a $41$ multiplexer that accepts $4$ input lines and $2$ selection lines. In Part B$,$ you will create an $81$ multiplexer that accepts $8$ input lines and $3$ selection lines.

a$.$ Create a Verilog file called mux$8$x$1.$v

i$.$ In it$,$ create a module called mux$\_8$x$1$ that accepts $11$ inputs called a$,$ b$,$ c$,$ d$,$ e$,$ f$,g,h,$ sel$0,$ sel$1,$ and sel$2$; and one output called out.

ii$.$ In the same way that you created your $41$ mux, use a set of nested ternary operators to construct your multiplexor that performs as follows:

If sel$2,$ sel$1,$ sel $0$

Modify the provided tb$.$v file to work as an $8$x$1$ multiplexor