In this particular register configuration, data is simultaneously inputted and outputted in parallel. All four flip

flops within the register are synchronized by both the clear $($CLR$)$ and clock signals. Input data is provided

individually to each flip flop, and similarly, output data is collected independently from each flip flop. This

setup exemplifies a $4-$bit Parallel In Parallel Out $($PIPO$)$ shift register.

Here is the $4-$ bit PIPO shift resister and sample module:

module four$\_$reg$($Q$,$Data,clk$)$;

parameter size $=4$;

input $[$size$-1$:$0]$D;

input clk;

output wire size$-1$:$0]$Q;

d$\_$ff Ul$($D$[0],$clk$,$Q$[0])$;

d$\_$ff U$2($D$[1],$clk$,$Q$[1])$;

d$\_$ff U$3($D$[2],$clk$,$Q$[2])$;

d$\_$ff U$4($D$[3],$clk$,$Q$[3])$;

endmodule

For the given data path in figure $4,$ you need to construct this type of hierarchical design for proper functionality

for the project.