Question: In Verilog code design a 2-bit multiplier with a enable signal, and only one instantiation of a 4-bit adder. If the enable signal is low,

In Verilog code design a 2-bit multiplier with a enable signal, and only one instantiation of a 4-bit adder. If the enable signal is low, then all the outputs should be held, but if the enable signal is high, then two 2-bit inputs should be multiplied every clock cycle. You need to sign extend your two 2-bit inputs to a full 4-bits and you can only use NAND gates to implement the decoder.

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