$`$include $"$prj$\_$definition.v$"$

module CONTROL$\_$UNIT$($MEM$\_$DATA, RF$\_$DATA$\_$W$,$ RF$\_$ADDR$\_$W$,$ RF$\_$ADDR$\_$R$1,$ RF$\_$ADDR$\_$R$2,$ RF$\_$READ, RF$\_$WRITE,

ALU$\_$OP$1,$ ALU$\_$OP$2,$ ALU$\_$OPRN, MEM$\_$ADDR, MEM$\_$READ, MEM$\_$WRITE,

RF$\_$DATA$\_$R$1,$ RF$\_$DATA$\_$R$2,$ ALU$\_$RESULT, ZERO, CLK$,$ RST$)$;

$//$ Output signals

$//$ Outputs for register file

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ RF$\_$DATA$\_$W;

output $[`$ADDRESS$\_$INDEX$\_$LIMIT:$0]$ RF$\_$ADDR$\_$W$,$ RF$\_$ADDR$\_$R$1,$ RF$\_$ADDR$\_$R$2$;

output RF$\_$READ, RF$\_$WRITE;

$//$ Outputs for ALU

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ ALU$\_$OP$1,$ ALU$\_$OP$2$;

output $[`$ALU$\_$OPRN$\_$INDEX$\_$LIMIT:$0]$ ALU$\_$OPRN;

$//$ Outputs for memory

output $[`$ADDRESS$\_$INDEX$\_$LIMIT:$0]$ MEM$\_$ADDR;

output MEM$\_$READ, MEM$\_$WRITE;

$//$ Input signals

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ RF$\_$DATA$\_$R$1,$ RF$\_$DATA$\_$R$2,$ ALU$\_$RESULT;

input ZERO, CLK$,$ RST;

$//$ Inout signal

inout $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ MEM$\_$DATA;

$//$ State nets

wire $[2$:$0]$ proc$\_$state;

PROC$\_$SM state$\_$machine$(.$STATE$($proc$\_$state$),.$CLK$($CLK$),.$RST$($RST$))$;

always @ $($proc$\_$state$)$

begin

$//$ TBD: Code for the control unit model

end

task print$\_$instruction;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ inst;

reg $[5$:$0]$ opcode;

reg $[4$:$0]$ rs;

reg $[4$:$0]$ rt;

reg $[4$:$0]$ rd;

reg $[4$:$0]$ shamt;

reg $[5$:$0]$ funct;

reg $[15$:$0]$ immediate;

reg $[25$:$0]$ address;

begin

$//$ parse the instruction

$//$ R$-$type

$\{$opcode$,$ rs$,$ rt$,$ rd$,$ shamt, funct$\}=$ inst;

$//$ I$-$type

$\{$opcode$,$ rs$,$ rt$,$ immediate $\}=$ inst;

$//$ J$-$type

$\{$opcode$,$ address$\}=$ inst;

$write$("$@ $\%6$dns $->[0$X$\%08$h$]",$ $time, inst$)$;

case$($opcode$)$

$//$ R$-$Type

$6\text{'}$h$00$ : begin

case$($funct$)$

$6\text{'}$h$20$: $write$("$add r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$22$: $write$("$sub r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$2$c: $write$("$mul r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$24$: $write$("$and r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$25$: $write$("$or r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$27$: $write$("$nor r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$2$a: $write$("$slt r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$01$: $write$("$sll r$\%02$d$,$ r$\%02$d$,0$X$\%02$h;$",$ rd$,$ rs$,$ shamt$)$;

$6\text{'}$h$02$: $write$("$srl r$\%02$d$,$ r$\%02$d$,0$X$\%02$h;$",$ rd$,$ rs$,$ shamt$)$;

$6\text{'}$h$08$: $write$("$jr r$\%02$d;$",$ rs$)$;

default: $write$("")$;

endcase

end

$//$ I$-$type

$6\text{'}$h$08$ : $write$("$addi r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$1$d : $write$("$muli r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$0$c : $write$("$andi r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$0$d : $write$("$ori r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$0$f : $write$("$lui r$\%02$d$,0$X$\%04$h;$",$ rt$,$ immediate$)$;

$6\text{'}$h$0$a : $write$("$slti r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$04$ : $write$("$beq r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$05$ : $write$("$bne r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$23$ : $write$("$lw r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$6\text{'}$h$2$b : $write$("$sw r$\%02$d$,$ r$\%02$d$,0$X$\%04$h;$",$ rt$,$ rs$,$ immediate$)$;

$//$ J$-$Type

$6\text{'}$h$02$ : $write$("$jmp $0$X$\%07$h;$",$ address$)$;

$6\text{'}$h$03$ : $write$("$jal $0$X$\%07$h;$",$ address$)$;

$6\text{'}$h$1$b : $write$("$push;$")$;

$6\text{'}$h$1$c : $write$("$pop;$")$;

default: $write$("")$;

endcase

$write$("$

$")$;

end

endtask

endmodule;

module PROC$\_$SM$($STATE$,$CLK$,$RST$)$;

$//$ list of inputs

input CLK$,$ RST;

$//$ list of outputs

output $[2$:$0]$ STATE;

$//$ TBD $-$ implement the state machine here

endmodule;