Instruction Pipelining w$/$ and w$/$o the Bypass Circuit:

Show the execution of the following sequence of MIPS instructions on the pipeline diagrams. Also show how each source operand of ALUs is gathered $($i$.$e$.$ read from the Register File at the Decode stage, forwarded from the first stage of the bypass circuit, etc.$).$ Assume that the Register File is dual$-$phase $($i$.$e$.$ writes are allowed in the first clock phase or the first half of the clock cycle, and reads are allowed at the second clock phase or at the second half of the same clock cycle$).$

I$1$: LOAD R$1,$ R$2,$ #$30//1$ cycle execute followed by $1$ cycle memory stage

I$2$: ADD R$4,$ R$5,$ R$1//1$ cycle execute stage

I$3$: MUL R$3,$ R$1,$ R$4//2$ cycle execute stage

I$4$: STORE R$4,$ R$3,$ #$10//1$ cycle execute followed by $1$ cycle memory stage

a$)$ No bypass circuit

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20],[$I$1,,,,,,,,,,,,,,,,,,,,],[$I$2,,,,,,,,,,,,,,,,,,,,]]$

b$)1-$stage half bypass circuit

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20],[$I$1,,,,,,,,,,,,,,,,,,,,],[$I$2,,,,,,,,,,,,,,,,,,,,]]$

$1$

c$)2-$stage full bypass circuit

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20],[$I$1,,,,,,,,,,,,,,,,,,,,]]$