integrate all modules to implement full Bus$-$based Datapath for RISC$-$V as described in the reference design.

$*$ you should use structural style; implement the Imm Gen module, and special purpose registers$($IR$,$ A$,$ B$,$ MA$).$

$*$ Datapath input : clock, control signals

$*$ Datapath output: status signals.

$*$ report should includes full documentation of each module with testing $($repeat what you have done in previous assignments$)$

$*$ report should include test$-$benches that simulate input coming from control unit.

$*$ report should include your ISA $($subset of risc$-$v ISA with some added features or addressing modes.$)$

$*$ test each instruction you have implemented

add micro$-$programmed control Unit to your datapath.

submit your code and updated report that includes all previous parts $+$ control unit documentation$($implementation$,$ test plans, testbench and waveforms$)$ USING VERILOG