is there a way to write this code more efficient using a loop for 'load' and 'read' from ram?

$--8$ Register Ram

$--$ Ram$\_8$Register$\_$SarahJohn

$--$ Created by John Sarah

library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$arith.all;

use ieee.std$\_$logic$\_$unsigned.all;

use ieee.numeric$\_$std$.$all;

entity Ram$\_8$Register$\_$SarahJohn is

port

$($

D : in std$\_$logic$\_$vector$(15$ downto $0)$;

Clock, Load : in std$\_$logic;

address : in std$\_$logic$\_$vector$(2$ downto $0)$;

Q : out std$\_$logic$\_$vector$(15$ downto $0)$

$)$;

end Ram$\_8$Register$\_$SarahJohn;

Architecture behavioral of Ram$\_8$Register$\_$SarahJohn is

type Array$8$x$16$ is array$(7$ downto $0)$ of std$\_$logic$\_$vector$(15$ downto $0)$;

signal RAM : Array$4$x$16$;

signal index : integer range $0$ to $7$;

Begin

process $($Clock$)$

Begin

if $($Rising$\_$edge$($CLock$))$ then

if $($Load $=\text{'}1\text{'})$ then

if address$=$B$"000"$ then RAM $(0)<=$D;

elsif address$=$B$"001"$ then RAM $(1)<=$D;

elsif address$=$B$"010"$ then RAM $(2)<=$D;

elsif address$=$B$"011"$ then RAM $(3)<=$D;

elsif address$=$B$"101"$ then RAM $(4)<=$D;

elsif address$=$B$"110"$ then RAM $(5)<=$D;

elsif address$=$B$"001"$ then RAM $(6)<=$D;

elsif address$=$B$"111"$ then RAM $(7)<=$D;

End if;

Q$<=$D;

else

if address$=$B$"000"$ then Q$<=$Ram $(0)$;

elsif address$=$B$"001"$ then Q$<=$RAM $(1)$;

elsif address$=$B$"010"$ then Q$<=$RAM $(2)$;

elsif address$=$B$"011"$ then Q$<=$RAM $(3)$;

elsif address$=$B$"100"$ then Q$<=$RAM $(4)$;

elsif address$=$B$"101"$ then Q$<=$RAM $(5)$;

elsif address$=$B$"110"$ then Q$<=$RAM $(6)$;

elsif address$=$B$"111"$ then Q$<=$RAM $(7)$;

end if;

end if;

end if;

end process;

end behavioral;