Just need help with the code and testbench I can do the simulations. Thanks.

VCSMX and SimVision Use generic (VHDL) statement to introduce small delay values at each stage of the data flow in your source code Circuit Description: The two input ports (A and B) are the 3-bit vector ports. The output ports (AeqB, AltB, AgtB) are single bit ports. The circuit compares the vector A with B. If A > B, then AeqB = 0, AltB = 0, and AgtB-1. Likewise, for A = B and A