Lab$3$: part $6$: Signed $\backslash$& Unsigned Comparator

Add a signal called US $($Unsigned$/$Signed$).$ When the signal is High $($Unsigned mode$),$ the Comparator interprets the numbers as Unsigned numbers. When the signal is Low $($Signed Mode$),$ the Comparator interprets the numbers as signed numbers. Example: in Verilog if you need $"$A$"$ be a signed value $==>\backslash$$signed $($A$).$

Activities:

$-$ Design the unsigned $3-$bit comparator above, using the "logical" operators

$-$ Add a signal $\text{'}$US$\text{'}$ as input to the design to make it be in unsigned or signed mode

$-$ Modify the $2-$bit comparator Verilog example below to design the $3-$bit comparator

Assignment:

$1.$ Test your Designs and compare your results with the expected results or truth tables. Note and explain any differences.

$2.$ Demo your results to Instructor

$3.$ In the Lab report include the following;

$-$ Verilog Design code for each Lab and a Test bench.

$-$ Comparison table of ModelSim waveform results $\backslash$& expected results $($Truth$-$table$).$