Lecture $09-$ Pipelined Processor Design

$1.$ Consider a $5-$stage instruction execution in which:

$$ Instruction fetch $=100$ ps

$$ ALU operation $=120$ ps

$$ Register read $=100$ ps

$$ Register write $=150$ ps

$$ Data memory access $=200$ ps

a$)$ What is the clock cycle of the single$-$cycle processor?

b$)$ What is the clock cycle of the pipelined processor?

c$)$ What is the speedup factor of pipelined execution?

$2.$ Define hazard. Mention the THREE types of pipeline hazards.

$($iii$)$ The following table shows the pipeline hazards we discussed. Fill the table by the cause of each hazard

and the techniques proposed to resolve it$.$

Hazard Cause Resolution Technique$($s$)$

Structural hazards

Data hazards

Control hazards