Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access =250ps; and Register read = Register write =200ps. Find out the speedup factor for pipelined execution. Question 9: Consider the timing diagram of Figure 1. Assume that there is only a five-stage pipelint (fetch, read, encode, execute, and write). Redraw the diagram to show how many time units are nov needed for ten instructions. Time, Figure 1: Timing Diagram for Instruction Pipeline Operation