Consider the $7-$stage pipelined processor with separate integer and Floating Point $($FP$)$ execution units and pipelined caches, as shown below. Along with the $32$ integer registers $0-431,$ there are $32$ additional Fil registers $10-131.$ Instruction fetch is a two$-$stage process $($F$1$ and F$2)$ followed by decode $(10)$ where registers are also read in the second half of the cycle. Additionally, the pipetine consists of a separate execution unit for floating puint operations. Integer execution unit, shown as the top branch, has a single stage $($EX$)$ and is used by all integer arithmetic $($excluding multiply$),$ load$/$store and branch instructions. FP execution unit, shown as the bottom branch, is also pipelined comprising three stages $($FP$-1,$ FP$-2$ and FP$-31,$ and is used by floating point $($FP$)$ add$/$sub and multiply $($for both integer and FP$)$ instructions. The two$-$stage pipelined data cache $($M$1$ and M$2)$ is used by Load and Store instructions for reading$/$writing integer and single precision floating point data. The final stage $($RW$)$ performs registers writes in the first half of the cycle, if required.

Consider the clock cycle time for the above pipeline to be $200$ ps$.$ Register $10$ is a hardwired zero but fo is not $0.$ All FP instructions are prefixed with T

be executed on this processor compared to the live stage RISC$-$V processor. Assume the

cycle time for RISC$-$VI: $350$ ps$,$ and no extra stall cycle, are inverted due to pipeline hazards.

Compute the latency of 'bne" Branch if Not Equal instruction Calculate the latency of single precision FP Add instruction 'fadd s Consider a program without FP and Multiplication instructions, compute how fast can it $12)$

What will happen if register writes sie perlurimed in ine second half of the cycle and reads $(2)$

in the first half?

For a program$-$A$,25\%$ Instructions are dependent floating$-$point instructions. Assuming no forwarding paths are available, calculate the addition to the CPI due to these hazards.

for a program$82\%$ions are branches dependent on an integer arithmetic jpeeding them and $5\%$ are branches ent dependent on a preceding Of $70\%$ are taken branches. Branch condition is evaluated in the EX$-$stage and beansh target address is computed in the stage. Again, assuming no forwarding paths are ausilatile, compute the addition to the CPI due to these hazards.

What types of hazends are present here? For the given processor, determine how many stall cydes are required between a load instruction and all the different classes of instructions that use the food's result during the

ewcution stag