This is questions.

blem 6114 pts]: Let's compare two different caches as shown below direct-mapped cache A and 2-way set-associative cache B Cache size Cache block size Page size Mapping Cache A 128 bytes 16 bytes 32 bytes Direct-Mapped Cache B 128 bytes 16 bytes 32 bytes 2-way set associative TLB is initialized like this table: PPN 0x09 0x19 0x29 0x39 0x49 0x59 VPN 0x10 VPN 0x07 0x09 0x09 0x0A OxOB Ox0C 0x30 0x11 0x21 0x31 PPN 0x69 0x79 0x89 0x99 OxA9 0xB9 Processor will access the memory with this virtual address sequence 0x144->0x15C-> ox100-> ox110-> 0x21C ox208 > Ox10c-> 0x114 (a) Assume the initial states of two caches as shown below. Find the final state of each caches after the given sequence. For cache B, assume it uses Least Recently Used (LRU) policy. Cache B Cache A Index Valid Tag Index Valid Tag(way0) Valid Tag(way 1) 0x1C 0x1C 0x24 0x24 10xE 1 OxE 10x12 7 1 0x12 0 blem 6114 pts]: Let's compare two different caches as shown below direct-mapped cache A and 2-way set-associative cache B Cache size Cache block size Page size Mapping Cache A 128 bytes 16 bytes 32 bytes Direct-Mapped Cache B 128 bytes 16 bytes 32 bytes 2-way set associative TLB is initialized like this table: PPN 0x09 0x19 0x29 0x39 0x49 0x59 VPN 0x10 VPN 0x07 0x09 0x09 0x0A OxOB Ox0C 0x30 0x11 0x21 0x31 PPN 0x69 0x79 0x89 0x99 OxA9 0xB9 Processor will access the memory with this virtual address sequence 0x144->0x15C-> ox100-> ox110-> 0x21C ox208 > Ox10c-> 0x114 (a) Assume the initial states of two caches as shown below. Find the final state of each caches after the given sequence. For cache B, assume it uses Least Recently Used (LRU) policy. Cache B Cache A Index Valid Tag Index Valid Tag(way0) Valid Tag(way 1) 0x1C 0x1C 0x24 0x24 10xE 1 OxE 10x12 7 1 0x12 0