List your answers using the same alphabet as the questions. Be brief and to the point....

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List your answers using the same alphabet as the questions. Be brief and to the point. You will lose marks if you write useless answers. 1. We have a direct-mapped cache with 4 locations and data memory with 8 locations. List the mapping of data memory locations to cache locations. [6] 2. Find the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls. [4] List your answers using the same alphabet as the questions. Be brief and to the point. You will lose marks if you write useless answers. 1. We have a direct-mapped cache with 4 locations and data memory with 8 locations. List the mapping of data memory locations to cache locations. [6] 2. Find the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls. [4]

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1 There are 4 2 cache locations thus the lowest 2 bits ... View the full answer