Looking at the diagram below, why is it important to add the latch to 10/M", RD', and W when it doesn't do any demultiplexing? (10 point) ION OE 244 IOVM RD WR Huffered control RD WR + OE Aws Ass Avs A. A. 373 A Aws G 8088 As As A As "244 AZ A Buffered address hus AD A A A A A, A, OE A A A A A A A ALE G 373 OE AD, AD AD AD. AD AD AD AD DTR DEN A B A R. A B A B A 245 B, A B A B B G DIR D. D. D D. D D D D. Buffered data bus | "Since AO is used to select the low bank of memory, we are only left with 19 bits of address and therefore we can only map 512KB of memory", do you agree with that statement and why? (10 point) In your opinion, what advantages do Separate Bank Write Strobe and Separate Bank Decoders have over each other? (10 point) JOM RD WR OE 244 JOM RD WR Buffered control bus OE A. At Aws Ae A. A 373 G 8088 As A. A A A A, A. As A A Buffered address bus A A, A, A A OL A. A A, A A A A ALE G 373 DEPZ AD AD A 8 A BA 4 B A B "245 A Az B A B A B G DIR AD AD AD AD AD AD DT/R DEN D D. D D. D D D D. Buttered data bus