6. Looking at the diagram below, why is it important to add the latch to IO/M, RD', and WR' when it doesn't do any demultiplexing? (10 point) OE IO/M RD WR 244 TO/M) Buffered RD control WR bus OE A1956 A18155 A17/54 A16/53 A, As A12 373 ALO G 8088 Als As A14 A4 244 A13 A2 AU A, A12 A, A As Buffered address bus A10 . A As OE A, As A A A2 A Ao ALE G 373 OE D D D DA AD AD ADS AD AD, AD AD AD. DT/R DEN A B A. , As BS A, B4 245 Az B A2 B2 A B A. B G DIR Buffered data bus D D