Question: Looking at the diagram below, why is it important to add the latch to IO/M, RD, and WR when it doesnt do any demultiplexing? (10

Looking at the diagram below, why is it important to add the latch to IO/M, RD, and WR when it doesnt do any demultiplexing? (10 point)

7 OE IOM RD WR IO/M RD WR Buffered control bus OE A95 Aless A17/54 AA 373 A, Ais A, ALE G 8088 As A, As AL A, Az '244 AI Buffered address bus A, 233 OE A A A. As A A, A A. ALE G 373 OE Z AD AD 245 A B As B B A B A, B A; B A, B B G DIR AD AD AD AD AD AD DT/R DEN D D. D D. D D. D D. Buffered data bus

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